20.
ISM manufacturing: prices in the 80s, but expansion continued
The manufacturing read separates alarming price pressure from continued expansion in orders and production
@SemiAnalysis_ on Backlist
23 appearances on the backlist front page in the last 30 days.
1.
NVIDIA open-sourced the Rubin NVSwitch tray BOM and diagrams
NVIDIA’s Rubin NVSwitch tray design exposes an AMD EPYC 3151 embedded CPU per tray, putting nine AMD CPUs inside each VR200 rack
12.
The case for space datacenters
Space datacenters become a cost question once terrestrial power, land, cooling, and chip-production constraints are modeled against launch and orbital operations
11.
SRAM scaling is hitting Cerebras’ wafer-scale roadmap
Cerebras’ wafer SRAM jumped 2.2x from WSE-1 to WSE-2 but only 10% on WSE-3, illustrating how SRAM scaling is becoming a hard limit for wafer-scale AI chips
41.
Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silic…
Cerebras did what the industry calls impossible: turned an entire 46,225mm² wafer into one chip. Defects on silicon that big are inevitable, so they built in redundancy and custom per-batch masks that route around every bad core, landing ne
13.
Memory chips are now 22% of South Korea’s exports
DRAM, SSDs, and HBM have grown from roughly 10% of Korean exports in 2018–2024 to 22% in 2026, overtaking autos by a wide margin
4.
CoreWeave and Dell report Rubin VR200 NVL72 racks passing L11 diagnostics
The first public Rubin rack bring-up signal marks a transition from NVIDIA roadmap slides to cloud-level software integration work
1.
AI may take 60% of TSMC N3 wafers in 2026 and 86% in 2027
Leading-edge accelerator supply is becoming a negotiation among TSMC, Apple, and Samsung rather than a normal capacity investment cycle
88.
The broader implication, which we work through in detail in the piece, is that the supply curve for frontier acce…
The broader implication, which we work through in detail in the piece, is that the supply curve for frontier accelerators is now effectively a policy decision inside two or three companies (TSMC, Apple, Samsung), not a capacity-investment q
1.
800VDC sidecars are coming for the data center
The move to 800VDC power distribution would rework data-center electrical architecture across roughly 39GW of expected incremental load
1.
Finding miscompiles for fun, not profit (t.co)
Compiler-fuzzing and model-assisted debugging can burn five figures in an afternoon while still surfacing real miscompilation bugs
3.
AI training clusters are turning onsite gas into the default power plan
US AI power demand is framed as jumping from about 3 GW in 2023 toward 28 GW by end-2026, faster than grid interconnect queues can absorb
33.
FACT ALERT : In modern agentic coding, 42% of the time is spent on CPU doing tool use such as editing files, run…
FACT ALERT : In modern agentic coding, 42% of the time is spent on CPU doing tool use such as editing files, running Bash scripts, running lints, etc. The economy of traditional cloud computing charges at $ per cpu core. In the economy of
1.
Agentic workloads are shifting inference economics toward 100k-token requests
SemiAnalysis measured 432k real coding-agent requests and found a 96k-token median input, making KV cache and long-context serving the next infrastructure bottleneck
34.
Even more striking: ~50% of requests already exceed 128k tokens. The driver isn't user prompts getting longer. It…
Even more striking: ~50% of requests already exceed 128k tokens. The driver isn't user prompts getting longer. It's everything the agent stuffs in before you even type: system prompts, tool definitions, skills, MCP schemas, prior turn conte
35.
Inference economics are shifting. Expect more "fast tier" pricing (Opus Fast, Gemini Flash), more specialized inf…
Inference economics are shifting. Expect more "fast tier" pricing (Opus Fast, Gemini Flash), more specialized inference hardware (Cerebras, Groq), and more pressure on KV cache management. The next bottleneck isn't model intelligence. It's
11.
Cheap CPU cloud servers are getting less cheap
CPU, DRAM, and storage scarcity is showing up in price increases from providers such as Hetzner, OVHcloud, and Scaleway
61.
If you’ve joined the vibe-coding wave (we certainly have!), one bottleneck you might have noticed is that the “ju…
If you’ve joined the vibe-coding wave (we certainly have!), one bottleneck you might have noticed is that the “just rent a cheap CPU box” step is no longer as routine as it used to be. (1/3)
3.
The Stop Stealing Our Chips Act would pay bounties for export-control violations
Chip export enforcement may gain a whistleblower market paying 10–30% of fines to people who report violations
5.
Google’s Broadfly TPU interconnect topology
Google’s inference-focused TPU pod uses a high-radix Broadfly ICI network with OCS layers to scale to 1,152 TPUs
75.
During their last Google Cloud Next conference in Las Vegas, Google unveiled their new inference-focused TPU, fea…
During their last Google Cloud Next conference in Las Vegas, Google unveiled their new inference-focused TPU, featuring a novel network topology called "Broadfly". By leveraging a high-radix design, Google can scale up to 1,152 TPUs in a si
85.
Let’s focus on the first for now; Assembly.
Let’s focus on the first for now; Assembly. Historically, packaging = low-margin wire bonding. Not exciting. ASE once made up ~40% of $KLIC’s wire bonder business. After the COVID boom, capacity flooded the market and growth stalled. (2/10
89.
But something is changing.
But something is changing. KLIC is now seeing : • 90%+ utilization in China And guiding to: • H2’26 China growth +15–20% vs H1 At the Chipbook we have been tracking wire bonder imports into China which are up +108% YoY in March. (3/10)